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d a t a sheet mos integr a ted circuit the m pd784036(a) is a product of the m pd784038 sub-series in the 78k/iv series. a stricter quality assurance program applies to the m pd784036(a) than the m pd784036 (standard product). in terms of the nec quality, the m pd784036(a) is classified as the special grade. the m pd784036(a) contains various peripheral hardware such as rom, ram, i/o ports, 8-bit resolution a/d and d/a converters, timers, serial interface, and interrupt functions, as well as a high-speed, high-performance cpu. in addition, the m pd78p4038(a) (one-time prom or eprom product), which can be operated within the same power supply voltage ranges as masked-rom products, and development tools are supported. for specific functions and other detailed information, consult the following users manual. this manual is required reading for design work. m pd784038, 784038y sub-series users manual, hardwar e : u11316e 78k/iv series users manual, instruction : u10905e features ? higher reliability than the m pd784036 (refer to qual- ity grade on nec semiconductor devices (document number c11531e).) ? minimum instruction execution time: 125 ns (at 32 mhz) ? number of i/o ports: 64 ? timer/counters 16-bit timer/counte r 3 units 16-bit time r 1 unit ? a/d converter: 8-bit resolutio n 8 channels ? d/a converter: 8-bit resolutio n 2 channels ? standby function halt/stop/idle mode applications controllers for automobile electronic control systems, gas detector circuit-breakers, various types of safety equipment, etc. this manual describes the m pd784036(a) unless otherwise specified. 1997 ? pwm outputs: 2 ? serial interface: 3 channels uart/ioe (3-wire serial i/o): 2 channels csi (3-wire serial i/o, 2-wire serial i/o): 1 channel ? clock frequency division function ? watchdog timer: 1 channel ? clock output function selected from f clk , f clk/ 2 , f clk/4 , f clk/8 , or f clk/16 ? power supply voltage: v dd = 2.7 to 5.5 v document no . u13010ej1v0ds00 (1st edition) date publishe d december 1997 j printed in japan 16/8-bit single-chip mic r ocont r oller the information in this document is subject to change without notice. m pd784035(a), 784036(a)
m pd784035(a), 784036(a) 2 ordering information part number package internal rom internal ram (bytes) (bytes) m pd784035gc(a)- -3b9 80-pin plastic qfp (14 14 mm) 48k 2 048 m pd784036gc(a)- -3b9 80-pin plastic qfp (14 14 mm) 64k 2 048 remark is a rom code suffix. quality grade part number package quality grade m pd784035gc(a)- -3b9 80-pin plastic qfp (14 14 mm) special m pd784036gc(a)- -3b9 80-pin plastic qfp (14 14 mm) special remark is a rom code suffix. please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications.
m pd784035(a), 784036(a) 3 78k/iv series product development diagram pd784026 pd784038y i 2 c bus supported pd784038 enhanced internal memory capacity, pin compatible with the pd784026 pd784225y multimaster i 2 c bus supported pd784225 80 pins, added rom correction pd784218y multimaster i 2 c bus supported multimaster i 2 c bus supported pd784218 enhanced internal memory capacity, added rom correction pd784928y multimaster i 2 c bus supported pd784928 enhanced function of the pd784915 pd784216y pd784054 pd784216 pd784046 pd784908 equipped with 10-bit a/d 100 pins, enhanced i/o and internal memory capacity enhanced a/d, 16-bit timer, and power management pd784915 for software servo control, equipped with analog circuit for vcr, enhanced timer equipped with iebus tm controller pd784943 for cd-rom standard models assp models : under mass production : under development m m m m m m m m m m m m m m pd784955 for dc inverter control m m m m m
m pd784035(a), 784036(a) 4 functions item m pd784035(a) rom ram total input input/output pins with pull- up resistor led direct drive outputs transistor direct drive 113 8 bits 16 registers 8 banks, or 16 bits 8 registers 8 banks (memory mapping) 125 ns/250 ns/500 ns/1 000 ns (at 32 mhz) 48k bytes 64k bytes 2 048 bytes program and data: 1m byte 64 8 56 54 24 8 4 bits 2, or 8 bits 1 timer/counter 0: timer register 1 pulse output capability (16 bits) capture register 1 toggle output compare register 2 pwm/ppg output one-shot pulse output timer/counter 1: timer register 1 pulse output capability (8/16 bits) capture register 1 real-time output (4 bits 2) capture/compare register 1 compare register 1 timer/counter 2: timer register 1 pulse output capability (8/16 bits) capture register 1 toggle output capture/compare register 1 pwm/ppg output compare register 1 timer 3 : timer register 1 (8/16 bits) compare register 1 12-bit resolution 2 channels uart/ioe (3-wire serial i/o) : 2 channels (incorporating baud rate generator) csi (3-wire serial i/o, 2-wire serial i/o): 1 channel 8-bit resolution 8 channels 8-bit resolution 2 channels selected from f clk , f clk /2, f clk /4, f clk /8, f clk /16 (can be used as a 1-bit output port) 1 channel halt/stop/idle mode 23 (16 internal, 7 external (sampling clock variable input: 1)) brk instruction, brkcs instruction, operand error 1 internal, 1 external 15 internal, 6 external 4-level programmable priority 3 operation statuses: vectored interrupt, macro service, context switching v dd = 2.7 to 5.5 v 80-pin plastic qfp (14 14 mm) number of basic instructions (mnemonics) general-purpose register minimum instruction execution time internal memory memory space i/o ports additional function pins note real-time output ports timer/counter pwm outputs serial interface a/d converter d/a converter clock output watchdog timer standby interrupt hardware source software source nonmaskable maskable supply voltage package note additional function pins are included in the i/o pins. product m pd784036(a)
m pd784035(a), 784036(a) 5 contents 1. differences between m pd784038 sub-series special products .................... 7 2. differences between standard and special products .................................. 7 3. pin configuration (top view) ......................................................................................... 8 4. block diagram ..................................................................................................................... 10 5. list of pin functions ......................................................................................................... 11 5.1 port pins ............................................................................................................................... ............. 11 5.2 non-port pins ............................................................................................................................... .... 13 5.3 i/o circuits for pins and handling of unused pins .................................................................... 15 6. cpu architecture ............................................................................................................... 18 6.1 memory space ............................................................................................................................... ... 18 6.2 cpu registers ............................................................................................................................... ... 21 6.2.1 general-purpose registers ................................................................................................ 21 6.2.2 control registers ................................................................................................................ 22 6.2.3 special function registers (sfrs) .................................................................................... 23 7. peripheral hardware functions ................................................................................ 28 7.1 ports ............................................................................................................................... .................... 28 7.2 clock generator ............................................................................................................................... 29 7.3 real-time output port ..................................................................................................................... 31 7.4 timers/counters ............................................................................................................................... 32 7.5 pwm output (pwm0, pwm1) .......................................................................................................... 34 7.6 a/d converter ............................................................................................................................... .... 35 7.7 d/a converter ............................................................................................................................... .... 36 7.8 serial interface ............................................................................................................................... .. 37 7.8.1 asynchronous serial interface/three-wire serial i/o (uart/ioe) ................................ 38 7.8.2 synchronous serial interface (csi) .................................................................................. 40 7.9 clock output function .................................................................................................................... 41 7.10 edge detection function ................................................................................................................ 42 7.11 watchdog timer ............................................................................................................................... 42 8. interrupt function ............................................................................................................ 43 8.1 interrupt source ............................................................................................................................... 43 8.2 vectored interrupt ............................................................................................................................ 45 8.3 context switching ............................................................................................................................ 46 8.4 macro service ............................................................................................................................... .... 46 8.5 examples of macro service applications ..................................................................................... 47
m pd784035(a), 784036(a) 6 9. local bus interface ......................................................................................................... 49 9.1 memory expansion .......................................................................................................................... 49 9.2 memory space ............................................................................................................................... ... 50 9.3 programmable wait ......................................................................................................................... 51 9.4 pseudo-static ram refresh function .......................................................................................... 51 9.5 bus hold function ........................................................................................................................... 51 10. standby function ............................................................................................................... 52 11. reset function ..................................................................................................................... 53 12. instruction set .................................................................................................................... 54 13. electrical characteristics ......................................................................................... 59 14. package drawings ............................................................................................................. 80 15. recommended soldering conditions ........................................................................ 81 appendix a development tools .......................................................................................... 82 appendix b related documents ......................................................................................... 85
m pd784035(a), 784036(a) 7 1. differences between m pd784038 sub-series special products the only difference between the m pd784031(a), m pd784035(a), and m pd784036(a) is their capacity of internal memory. the m pd78p4038(a) is produced by replacing the masked rom in the m pd784031(a), m pd784035(a), or m pd784036(a) with 128k-byte one-time prom or eprom. table 1-1 shows the differences between these products. table 1-1. differences between the m pd784038 sub-series special products 2. differences between standard and special products table 2-1 shows the differences between standard and special products. table 2-1. differences between standard and special products product item internal rom internal ram m pd784035(a) 48k bytes (masked rom) 2 048 bytes m pd784031(a) none m pd784036(a) 64k bytes (masked rom) m pd78p4038(a) (under develoment) 128k bytes (one-time prom or eprom) 4 352 bytes product item quality grade package m pd784035, m pd784036, m pd784037, m pd784038 m pd784035(a), m pd784036(a) special 80-pin plastic qfp (14 14 2.7 mm) standard 80-pin plastic qfp (14 14 2.7 mm) 80-pin plastic qfp (14 14 1.4 mm) 80-pin plastic tqfp (fine pitch, 12 12 mm)
m pd784035(a), 784036(a) 8 3. pin configuration (top view) ? 80-pin plastic qfp (14 14 mm) m pd784031gc(a)- -3b9, m pd784036gc(a)- -3b9 note connect the test pin to v ss0 directly. 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 p74/ani4 p73/ani3 p72/ani2 p71/ani1 p70/ani0 v dd0 p17 p16 p15 p14/t x d2/so2 p13/r x d2/si2 p12/asck2/sck2 p11/pwm1 p10/pwm0 test note v ss0 astb/clkout p40/ad0 p41/ad1 p42/ad2 p32/sck0/scl p33/so0/sda p34/ to0 p35/ to1 p36/ to2 p37/ to3 reset v dd1 x2 x1 v ss1 p00 p01 p02 p03 p04 p05 p06 p07 p67/refrq/hldak p66/ wait/hldrq p65/wr p64/rd p63/a19 p62/a18 p61/a17 p60/a16 p57/a15 p56/a14 p55/a13 p54/a12 p53/a11 p52/a10 p51/a9 p50/a8 p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p31/ txd/so1 p30/rxd/si1 p27/si0 p26/intp5 p25/intp4/asck/sck1 p24/intp3 p23/intp2/ci p22/intp1 p21/intp0 p20/nmi av ref3 av ref2 ano1 ano0 av ss av ref1 av dd p77/ani7 p76/ani6 p75/ani5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
m pd784035(a), 784036(a) 9 p60-p67 : port 6 p70-p77 : port 7 pwm0, pwm1 : pulse width modulation output rd : read strobe refrq : refresh request reset : reset rxd, rxd2 : receive data sck0-sck2 : serial clock scl : serial clock sda : serial data si0-si2 : serial input so0-so2 : serial output test : test to0-to3 : timer output txd, txd2 : transmit data v dd0 , v dd1 : power supply v ss0 , v ss1 : ground wait : wait wr : write strobe x1, x2 : crystal a8-a19 : address bus ad0-ad7 : address/data bus ani0-ani7 : analog input ano0, ano1 : analog output asck, asck2 : asynchronous serial clock astb : address strobe av dd : analog power supply av ref1 -av ref3 : reference voltage av ss : analog ground ci : clock input clkout : clock output hldak : hold acknowledge hldrq : hold request intp0-intp5 : interrupt from peripherals nmi : non-maskable interrupt p00-p07 : port 0 p10-p17 : port 1 p20-p27 : port 2 p30-p37 : port 3 p40-p47 : port 4 p50-p57 : port 5
m pd784035(a), 784036(a) 10 4. block diagram remark the internal rom capacity differs for each product. nmi intp3 to0 to1 intp0 intp1 intp2/ci to2 to3 p00-p03 p04-p07 pwm0 pwm1 ano0 ano1 av ref2 av ref3 intp5 ani0-ani7 txd/so1 asck/sck1 rxd/si1 asck2/sck2 sck0/scl so0/sda si0 a8-a15 p00-p07 p20-p27 p10-p17 p30-p37 p70-p77 astb/clkout refrq/hldak wr wait/hldrq ad0-ad7 rd a16-a19 x1 x2 reset test v dd0 , v dd1 v ss0 , v ss1 av dd av ref1 av ss uart/ioe2 uart/ioe1 baud-rate generator clock output clocked serial interface bus interface port 0 port 1 port 2 port 3 port 7 system control programmable interrupt controller timer/counter 0 timer/counter 1 timer/counter 2 timer 3 real-time output port pwm d /a converter a /d converter intp0-intp5 (16 bits) (16 bits) (16 bits) (16 bits) 78k /iv cpu core watchdog timer baud-rate generator txd2/so2 rxd2/si2 p40-p47 port 4 p50-p57 port 5 p60-p67 port 6 ram rom
m pd784035(a), 784036(a) 11 5. list of pin functions 5.1 port pins (1/2) function port 0 (p0): 8-bit i/o port. functions as a real-time output port (4 bits 2). inputs and outputs can be specified bit by bit. the use of the pull-up resistors can be specified by software for the pins in input mode together. can drive a transistor. port 1 (p1): 8-bit i/o port. inputs and outputs can be specified bit by bit. the use of the pull-up resistors can be specified by software for the pins in input mode together. can drive led. port 2 (p2): 8-bit input-only port. p20 does not function as a general-purpose port (nonmaskable interrupt). however, the input level can be checked by an interrupt service routine. the use of the pull-up resistors can be specified by software for pins p22 to p27 (in units of 6 bits). the p25/intp4/asck/sck1 pin functions as the sck1 output pin by csim1. port 3 (p3): 8-bit i/o port. inputs and outputs can be specified bit by bit. the use of the pull-up resistors can be specified by software for the pins in input mode together. port 4 (p4): 8-bit i/o port. inputs and outputs can be specified bit by bit. the use of the pull-up resistors can be specified by software for the pins in the input mode together. can drive led. port 5 (p5): 8-bit i/o port. inputs and outputs can be specified bit by bit. the use of the pull-up resistors can be specified by software for the pins in the input mode together. can drive led. pin p00-p07 p10 p11 p12 p13 p14 p15-p17 p20 p21 p22 p23 p24 p25 p26 p27 p30 p31 p32 p33 p34-p37 p40-p47 p50-p57 i/o i/o i/o input i/o i/o i/o dual-function - pwm0 pwm1 asck2/sck2 rxd2/si2 txd2/so2 - nmi intp0 intp1 intp2/ci intp3 intp4/asck/sck1 intp5 si0 rxd/si1 txd/so1 sck0/scl so0/sda to0-to3 ad0-ad7 a8-a15
m pd784035(a), 784036(a) 12 5.1 port pins (2/2) function port 6 (p6): 8-bit i/o port. inputs and outputs can be specified bit by bit. the use of the pull-up resistors can be specified by software for the pins in the input mode together. port 7 (p7): 8-bit i/o port. inputs and outputs can be specified bit by bit. pin p60-p63 p64 p65 p66 p67 p70-p77 i/o i/o i/o dual-function a16-a19 rd wr wait/hldrq refrq/hldak ani0-ani7
m pd784035(a), 784036(a) 13 pin i/o dual-function function to0-to3 output p34-p37 timer output ci input p23/intp2 input of a count clock for timer/counter 2 r x d input p30/si1 serial data input (uart0) r x d2 p13/si2 serial data input (uart2) t x d output p31/so1 serial data output (uart0) t x d2 p14/so2 serial data output (uart2) asck input p25/intp4/sck1 baud rate clock input (uart0) asck2 p12/sck2 baud rate clock input (uart2) sda i/o p33/so0 serial data i/o (2-wire serial i/o) si0 input p27 serial data input (3-wire serial i/o0) si1 p30/r x d serial data input (3-wire serial i/o1) si2 p13/r x d2 serial data input (3-wire serial i/o2) so0 output p33/sda serial data output (3-wire serial i/o0) so1 p31/t x d serial data output (3-wire serial i/o1) so2 p14/t x d2 serial data output (3-wire serial i/o2) sck0 i/o p32/scl serial clock i/o (3-wire serial i/o0) sck1 p25/intp4/asck serial clock i/o (3-wire serial i/o1) sck2 p12/asck2 serial clock i/o (3-wire serial i/o2) scl p32/sck0 serial clock i/o (2-wire serial i/o) nmi input p20 - intp0 p21 input of a count clock for timer/counter 1 capture/trigger signal for cr11 or cr12 intp1 p22 input of a count clock for timer/counter 2 capture/trigger signal for cr22 intp2 p23/ci input of a count clock for timer/counter 2 capture/trigger signal for cr21 intp3 p24 input of a count clock for timer/counter 0 capture/trigger signal for cr02 intp4 p25/asck/sck1 - intp5 p26 input of a conversion start trigger for a/d converter ad0-ad7 i/o p40-p47 time multiplexing address/data bus (for connecting external memory) a8-a15 output p50-p57 high-order address bus (for connecting external memory) a16-a19 output p60-p63 high-order address bus during address expansion (for connecting external memory) rd output p64 strobe signal output for reading the contents of external memory wr output p65 strobe signal output for writing on external memory wait input p66/hldrq wait signal insertion refrq output p67/hldak refresh pulse output to external pseudo static memory hldrq input p66/wait input of bus hold request hldak output p67/refrq output of bus hold response astb output clkout latch timing output of time multiplexing address (a0-a7) (for connecting external memory) clkout output astb clock output 5.2 non-port pins (1/2) external interrupt reguest
m pd784035(a), 784036(a) 14 5.2 non-port pins (2/2) notes 1. the potential of the v dd0 pin must be equal to that of the v dd1 pin. 2. the potential of the v ss0 pin must be equal to that of the v ss1 pin. pin reset x1 x2 ani0-ani7 ano0, ano1 av ref1 av ref2 , av ref3 av dd av ss v dd0 note 1 v dd1 note 1 v ss0 note 2 v ss1 note 2 test i/o input input - input output - function chip reset crystal input for system clock oscillation (a clock pulse can also be input to the x1 pin.) analog voltage inputs for the a/d converter analog voltage outputs for the d/a converter application of a/d converter reference voltage application of d/a converter reference voltage positive power supply for the a/d converter ground for the a/d converter positive power supply of the port part positive power supply except for the port part ground of the port part ground except for the port part directly connect to v ss0 . (the test pin is for the ic test.) dual-function - - p70-p77 - -
m pd784035(a), 784036(a) 15 5.3 i/o circuits for pins and handling of unused pins table 5-1 describes the types of i/o circuits for pins and the handling of unused pins. see figure 5-1 for the configuration of these various types of i/o circuits. table 5-1. types of i/o circuits for pins and handling of unused pins (1/2) pin i/o circuit type i/o recommended connection method for unused pins p00-p07 5-h i/o input state : connect these pins to v dd0 . p10/pwm0 output state: leave open. p11/pwm1 p12/asck2/sck2 8-c p13/rxd2/si2 5-h p14/txd2/so2 p15-p17 p20/nmi 2 input connect these pins to v dd0 or v ss0 . p21/intp0 p22/intp1 2-c connect these pins to v dd0 . p23/intp2/ci p24/intp3 p25/intp4/asck/sck1 8-c i/o input state : connect these pins to v dd0 . output state: leave open. p26/intp5 2-c input connect these pins to v dd0 . p27/si0 p30/rxd/si1 5-h i/o input state : connect these pins to v dd0 . p31/txd/so1 output state: leave open. p32/sck0/scl 10-b p33/so0/sda p34/to0-p37/to3 5-h p40/ad0-p47/ad7 p50/a8-p57/a15 p60/a16-p63/a19 p64/rd p65/wr p66/wait/hldrq p67/refrq/hldak p70/ani0-p77/ani7 20-a i/o input state : connect these pins to v dd0 or v ss0 . output state: leave open. ano0, ano1 12 output leave open. astb/clkout 4-b
m pd784035(a), 784036(a) 16 table 5-1. types of i/o circuits for pins and handling of unused pins (2/2) pin i/o circuit type i/o recommended connection method for unused pins reset 2 input - test 1-a connect this pin to v ss0 directly. av ref1 -av ref3 - connect these pins to v ss0 . av ss av dd connect this pin to v dd0 . caution when i/o mode of an i/o dual-function pin is unpredictable, connect the pin to v dd0 through a resistor of 10 to 100 kilohms (particularly when the voltage of the reset input pin becomes higher than that of the low level input at power-on or when i/o is switched by software). remark since type numbers are consistent in the 78k series, those numbers are not always serial in each product. (some circuits are not included.)
m pd784035(a), 784036(a) 17 figure 5-1. i/o circuits for pins type 1-a type 2-c type 2 type 4-b type 8-c type 10-b type 5-h type 12 type 20-a in schmitt trigger input with hysteresis characteristics n p analog output voltage out in v dd0 v ss0 p n schmitt trigger input with hysteresis characteristics in v dd0 p pull-up enable data v dd0 v ss0 p n out output disable push-pull output which can output high impedance (both the positive and negative channels are off.) data v dd0 v ss0 p n in/out output disable v dd0 p pull-up enable input enable data v dd0 p n in/out output disable v dd0 v ss0 p pull-up enable data v dd0 p n in/out output disable v dd0 v ss0 p pull-up enable open drain data comparator v dd0 v ss0 av ref av ss p (threshold voltage) p n n in/out output disable input enable +
m pd784035(a), 784036(a) 18 6. cpu architecture 6.1 memory space a 1m-byte memory space can be accessed. by using a location instruction, mode for mapping internal data areas (special function registers and internal ram) can be selected. a location instruction must always be executed after a reset, and can be used only once. (1) when the location 0 instruction is executed ? internal memory the table below indicates the internal data areas and internal rom areas of each product. caution the following internal rom areas, existing at the same addresses as the internal data areas, cannot be used when the location 0 instruction is executed: ? external memory external memory is accessed in external memory expansion mode. (2) when the location 0fh instruction is executed ? internal memory the table below lists the internal data areas and internal rom areas for each product. ? external memory external memory is accessed in external memory expansion mode. product name unusable area m pd784035(a) - m pd784036(a) 0f700h-0ffffh (2 304 bytes) product name internal data area internal rom area m pd784035(a) 0f700h-0ffffh 00000h-0bfffh m pd784036(a) 00000h-0f6ffh product name internal data area internal rom area m pd784035(a) ff700h-fffffh 00000h-0bfffh m pd784036(a) 00000h-0ffffh
m pd784035(a), 784036(a) 19 figure 6-1. m pd784035(a) memory map notes 1. accessed in external memory expansion mode. 2. base area, or entry area based on a reset or interrupt. internal ram is excluded in the case of a reset. ffeffh ffeffh fff ffh fff dfh fff d0h fff 00h ffe 80h ffe 7fh ff7 00h ff6 ffh 100 00h 0ffffh 0c0 00h 0bf ffh 000 00h ffe 2fh ffe 06h ffd00h ffcffh ff7 00h when the location 0 instruction is executed external memory (960k bytes) note 1 special function registers (sfrs) note 1 (256 bytes) internal ram (2 048 bytes) note 2 external memory (14 080 bytes) note 1 internal rom (48k bytes) 0 fffh e 0 f80h e 0 f7fh e 0 f00h d 0 fffh c 0 100h 0 0 0ffh f 0 000h 8 0 0ffh 7 0 080h 0 0 07fh 0 0 040h 0 0 03fh 0 0 000h 0 0 f00h 7 0 bffh f 0 f2fh e 0 f06h e f fffh f 0 fffh f 1 000h 0 0 fdfh f 0 fd0h f 0 f00h f 0 fffh e 0 f00h 7 0 fffh 6 0 c00h 0 0 bffh f 0 000h 0 note 2 general-purpose registers (128 bytes) macro service control word area (42 bytes) data area (512 bytes) program/data area (1 536 bytes) program/data area (48k bytes) callf entry area (2k bytes) callt table area (64 bytes) vector table area (64 bytes) when the location 0fh instruction is executed special function registers (sfrs) (256 bytes) note 1 internal ram (2 048 bytes) external memory (997 120 bytes) note 1 internal rom (48k bytes)
m pd784035(a), 784036(a) 20 figure 6-2. m pd784036(a) memory map notes 1. accessed in external memory expansion mode. 2. this 2304-byte area can be used as an internal rom area only when the location 0fh instruction is executed. 3. when the location 0 instruction is executed : 63 232 bytes when the location 0fh instruction is executed: 65 536 bytes 4. base area, or entry area based on a reset or interrupt. internal ram is excluded in the case of a reset. fffffh 0 ffffh 0ffdfh 0ffd0h 0ff00h 0feffh 10000h 0f700h 0f6ffh 00000h 0feffh 0fe80h 0fe7fh 0fe2fh 0fe06h 0fd00h 0 fcffh 0f700h 0f6ffh 01000h 00fffh 00800h 007ffh 00080h 0007fh 00040h 0003fh 00000h ffeffh ffe80h ffe7fh ffe2fh ffe06h ffd00h f fcffh ff700h 0 ffffh 10000h 0 ffffh 00000h ff6ffh ff700h ffeffh fff00h fffd0h fffdfh f ffffh when the location 0 instruction is executed external memory (960k bytes) note 1 special function registers (sfrs) note 1 (256 bytes) internal ram (2 048 bytes) note 4 internal rom (63 232 bytes) general-purpose registers (128 bytes) macro service control word area (42 bytes) data area (512 bytes) program/data area (1 536 bytes) program/data area note 3 note 2 callf entry area (2k bytes) callt table area (64 bytes) vector table area (64 bytes) internal rom (64k bytes) note 4 external memory (980 736 bytes) note 1 when the location 0fh instruction is executed special function registers (sfrs) (256 bytes) internal ram (2 048 bytes) note 1
m pd784035(a), 784036(a) 21 6.2 cpu registers 6.2.1 general-purpose registers a set of general-purpose registers consists of sixteen general-purpose 8-bit registers. two 8-bit general-purpose registers can be combined to form a 16-bit general-purpose register. moreover, four 16-bit general-purpose registers, when combined with an 8-bit register for address extension, can be used as 24-bit address specification registers. eight banks of this register set are provided. the user can switch between banks by software or the context switching function. general-purpose registers other than the v, u, t, and w registers used for address extension are mapped onto internal ram. figure 6-3. general-purpose register format a (r1) x (r0) b (r3) c (r2) r5 r4 r7 r6 r9 r8 r11 r10 d (r13) e (r12) h (r15) v u t w l (r14) ax (rp0) bc (rp1) rp2 rp3 vp (rp4) up (rp5) de (rp6) hl (rp7) vvp (rg4) uup (rg5) tde (rg6) whl (rg7) the character strings enclosed in parentheses represent absolute names. 8 banks caution by setting the rss bit of psw to 1, r4, r5, r6, r7, rp2, and rp3 can be used as the x, a, c, b, ax, and bc registers, respectively. however, this function must be used only when using programs for the 78k/iii series.
m pd784035(a), 784036(a) 22 6.2.2 control registers (1) program counter (pc) this register is a 20-bit program counter. the program counter is automatically updated by program execution. figure 6-4. format of program counter (pc) 19 0 pc (2) program status word (psw) this register holds the cpu state. the program status word is automatically updated by program execution. figure 6-5. format of program status word (psw) pswh pswl psw 15 14 13 12 uf rbs2 rbs1 rbs0 11 10 9 8 76543210 s z rss note ac ie p/v 0 cy note this flag is used to maintain compatibility with the 78k/iii series. this flag must be set to 0 when programs for the 78k/iii series are being used. (3) stack pointer (sp) this register is a 24-bit pointer for holding the start address of the stack. the high-order 4 bits must be set to 0. figure 6-6. format of stack pointer (sp) 23 20 0 sp 0 0 0 0
m pd784035(a), 784036(a) 23 6.2.3 special function registers (sfrs) the special function registers are registers with special functions such as mode registers and control registers for built-in peripheral hardware. the special function registers are mapped onto the 256-byte space between 0ff00h and 0ffffh note . note applicable when the location 0 instruction is executed. fff00h-fffffh when the location 0fh instruction is executed. caution never attempt to access addresses in this area where no sfr is allocated. otherwise, the m pd784036(a) may be placed in the deadlock state. the deadlock state can be cleared only by a reset. table 6-1 lists the special function registers (sfrs). the titles of the table columns are explained below. ? abbreviation ................... symbol used to represent a built-in sfr. the abbreviations listed in the table are reserved words for the nec assembler (ra78k4). the c compiler (cc78k4) allows the abbreviations to be used as sfr variables with the #pragma sfr command. ? r/w ................................. indicates whether each sfr allows read and/or write operations. r/w : allows both read and write operations. r : allows read operations only. w : allows write operations only. ? manipulatable bits .......... indicates the maximum number of bits that can be manipulated whenever an sfr is manipulated. an sfr that supports 16-bit manipulation can be described in the sfrp operand. for address specification, an even-numbered address must be speci- fied. an sfr that supports 1-bit manipulation can be described in a bit manipulation instruction. ? when reset ..................... indicates the state of each register when reset is applied.
m pd784035(a), 784036(a) 24 table 6-1. special function registers (sfrs) (1/4) address note special function register (sfr) name abbreviation r/w manipulatable bits when reset 1 bit 8 bits 16 bits 0ff00h port 0 p0 r/w - undefined 0ff01h port 1 p1 - 0ff02h port 2 p2 r - 0ff03h port 3 p3 r/w - 0ff04h port 4 p4 - 0ff05h port 5 p5 - 0ff06h port 6 p6 - 00h 0ff07h port 7 p7 - undefined 0ff0eh port 0 buffer register l p0l - 0ff0fh port 0 buffer register h p0h - 0ff10h compare register (timer/counter 0) cr00 - - 0ff12h capture/compare register (timer/counter 0) cr01 - - 0ff14h compare register l (timer/counter 1) cr10 cr10w - 0ff15h compare register h (timer/counter 1) - - - 0ff16h capture/compare register l (timer/counter 1) cr11 cr11w - 0ff17h capture/compare register h (timer/counter 1) - - - 0ff18h compare register l (timer/counter 2) cr20 cr20w - 0ff19h compare register h (timer/counter 2) - - - 0ff1ah capture/compare register l (timer/counter 2) cr21 cr21w - 0ff1bh capture/compare register h (timer/counter 2) - - - 0ff1ch compare register l (timer 3) cr30 cr30w - 0ff1dh compare register h (timer 3) - - - 0ff20h port 0 mode register pm0 - ffh 0ff21h port 1 mode register pm1 - 0ff23h port 3 mode register pm3 - 0ff24h port 4 mode register pm4 - 0ff25h port 5 mode register pm5 - 0ff26h port 6 mode register pm6 - 0ff27h port 7 mode register pm7 - 0ff2eh real-time output port control register rtpc - 00h 0ff30h capture/compare control register 0 crc0 - - 10h 0ff31h timer output control register toc - 00h 0ff32h capture/compare control register 1 crc1 - - 0ff33h capture/compare control register 2 crc2 - - 10h note applicable when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h is added to each address.
m pd784035(a), 784036(a) 25 table 6-1. special function registers (sfrs) (2/4) address note 1 special function register (sfr) name abbreviation r/w manipulatable bits when reset 1 bit 8 bits 16 bits 0ff36h capture register (timer/counter 0) cr02 r - - 0000h 0ff38h capture register l (timer/counter 1) cr12 cr12w - 0ff39h capture register h (timer/counter 1) - - - 0ff3ah capture register l (timer/counter 2) cr22 cr22w - 0ff3bh capture register h (timer/counter 2) - - - 0ff41h port 1 mode control register pmc1 r/w - 00h 0ff43h port 3 mode control register pmc3 - 0ff4eh register for optional pull-up resistor puo - 0ff50h timer register 0 tm0 r note 2 -- 0000h 0ff51h -- 0ff52h timer register 1 tm1 tm1w - 0ff53h - - - 0ff54h timer register 2 tm2 tm2w - 0ff55h - - - 0ff56h timer register 3 tm3 tm3w - 0ff57h - - - 0ff5ch prescaler mode register 0 prm0 r/w - - 11h 0ff5dh timer control register 0 tmc0 - 00h 0ff5eh prescaler mode register 1 prm1 - - 11h 0ff5fh timer control register 1 tmc1 - 00h 0ff60h d/a conversion value setting register 0 dacs0 - - 0ff61h d/a conversion value setting register 1 dacs1 - - 0ff62h d/a converter mode register dam - 03h 0ff68h a/d converter mode register adm - 00h 0ff6ah a/d conversion result register adcr r - - undefined 0ff70h pwm control register pwmc r/w - 05h 0ff71h pwm prescaler register pwpr - - 00h 0ff72h pwm modulo register 0 pwm0 - - undefined 0ff74h pwm modulo register 1 pwm1 - - 0ff7dh one-shot pulse output control register ospc - 00h 0ff80h i 2 c bus control register iicc - 0ff81h prescaler mode register for serial clock sprm - - 04h 0ff82h synchronous serial interface mode register csim - 00h notes 1. applicable when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h is added to each address. 2. some registers cannot read. refer to the m pd78038, m pd784038y sub-series users manual, hardware for details.
m pd784035(a), 784036(a) 26 address note 1 special function register (sfr) name abbreviation r/w manipulatable bits when reset 1 bit 8 bits 16 bits 0ff84h synchronous serial interface mode register 1 csim1 r/w - 00h 0ff85h synchronous serial interface mode register 2 csim2 - 0ff86h serial shift register sio - - 0ff88h asynchronous serial interface mode register asim - 0ff89h asynchronous serial interface mode register 2 asim2 - 0ff8ah asynchronous serial interface status register asis r - 0ff8bh asynchronous serial interface status register 2 asis2 - 0ff8ch serial receive buffer: uart0 rxb - - undefined serial transmission shift register: uart0 txs w - - serial shift register: ioe1 sio1 r/w - - 0ff8dh serial receive buffer: uart2 rxb2 r - - serial transmission shift register: uart2 txs2 w - - serial shift register: ioe2 sio2 r/w - - 0ff90h baud rate generator control register brgc - - 00h 0ff91h baud rate generator control register 2 brgc2 - - 0ffa0h external interrupt mode register 0 intm0 - 0ffa1h external interrupt mode register 1 intm1 - 0ffa4h sampling clock selection register scs0 - - 0ffa8h in-service priority register ispr r - 0ffaah interrupt mode control register imc r/w - 80h 0ffach interrupt mask register 0l mk0l mk0 ffffh 0ffadh interrupt mask register 0h mk0h 0ffaeh interrupt mask register 1l mk1l - ffh 0ffc0h standby control register stbc - note 2 - 30h 0ffc2h watchdog timer mode register wdm - note 2 - 00h 0ffc4h memory expansion mode register mm - 20h 0ffc5h hold mode register hldm - 00h 0ffc6h clock output mode register clom - 0ffc7h programmable wait control register 1 pwc1 - - aah 0ffc8h programmable wait control register 2 pwc2 - - aaaah table 6-1. special function registers (sfrs) (3/4) notes 1. applicable when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h is added to each address. 2. a write operation can be performed only with special instructions mov stbc, #byte and mov wdm,#byte. other instructions cannot perform a write operation.
m pd784035(a), 784036(a) 27 table 6-1. special function registers (sfrs) (4/4) note applicable when the location 0 instruction is executed. when the location 0fh instruction is executed, f0000h is added to each address. address note special function register (sfr) name abbreviation r/w manipulatable bits when reset 1 bit 8 bits 16 bits 0ffcch refresh mode register rfm r/w - 00h 0ffcdh refresh area specification register rfa - 0ffcfh oscillation settling time specification register osts - - 0ffd0h- external sfr area - - - 0ffdfh 0ffe0h interrupt control register (intp0) pic0 - 43h 0ffe1h interrupt control register (intp1) pic1 - 0ffe2h interrupt control register (intp2) pic2 - 0ffe3h interrupt control register (intp3) pic3 - 0ffe4h interrupt control register (intc00) cic00 - 0ffe5h interrupt control register (intc01) cic01 - 0ffe6h interrupt control register (intc10) cic10 - 0ffe7h interrupt control register (intc11) cic11 - 0ffe8h interrupt control register (intc20) cic20 - 0ffe9h interrupt control register (intc21) cic21 - 0ffeah interrupt control register (intc30) cic30 - 0ffebh interrupt control register (intp4) pic4 - 0ffech interrupt control register (intp5) pic5 - 0ffedh interrupt control register (intad) adic - 0ffeeh interrupt control register (intser) seric - 0ffefh interrupt control register (intsr) sric - interrupt control register (intcsi1) csiic1 - 0fff0h interrupt control register (intst) stic - 0fff1h interrupt control register (intcsi) csiic - 0fff2h interrupt control register (intser2) seric2 - 0fff3h interrupt control register (intsr2) sric2 - interrupt control register (intcsi2) csiic2 - 0fff4h interrupt control register (intst2) stic2 -
m pd784035(a), 784036(a) 28 7. peripheral hardware functions 7.1 ports the ports shown in figure 7-1 are provided to enable the application of wide-ranging control. table 7-1 lists the functions of the ports. for the inputs to port 0 to port 6, a built-in pull-up resistor can be specified by software. figure 7-1. port configuration port 0 p00 p07 8 port 4 p40 p47 port 1 p10 p17 port 2 p20-p27 port 3 p30 p37 port 5 p50 p57 port 6 p60 p67 port 7 p70 p77
m pd784035(a), 784036(a) 29 table 7-1. port functions 7.2 clock generator a circuit for generating the clock signal required for operation is provided. the clock generator includes a frequency divider; low current consumption can be achieved by operating at a lower internal frequency when high-speed operation is not necessary. figure 7-2. block diagram of clock generator remark f xx : oscillator frequency or external clock input f clk : internal operating frequency port name pin function pull-up specification by software port 0 p00-p07 ? bit-by-bit input/output setting supported specified as a batch for all pins placed in ? operable as 4-bit real-time outputs input mode. (p00-p03, p04-p07) ? capable of driving transistors port 1 p10-p17 ? bit-by-bit input/output setting supported specified as a batch for all pins placed in ? capable of driving leds input mode. port 2 p20-p27 ? input port specified for the 6 bits (p22-p27) as a batch. port 3 p30-p37 ? bit-by-bit input/output setting supported specified as a batch for all pins placed in input mode. port 4 p40-p47 ? bit-by-bit input/output setting supported specified as a batch for all pins placed in ? capable of driving leds input mode. port 5 p50-p57 ? bit-by-bit input/output setting supported specified as a batch for all pins placed in ? capable of driving leds input mode. port 6 p60-p67 ? bit-by-bit input/output setting supported specified as a batch for all pins placed in input mode. port 7 p70-p77 ? bit-by-bit input/output setting supported - x1 x2 f xx /2 f xx f clk cpu peripheral circuits oscillator uart/ioe intp0 noise eliminator oscillation settling timer selector 1/2 1/2 1/2 1/2
m pd784035(a), 784036(a) 30 figure 7-3. examples of using oscillator (1) crystal/ceramic oscillation v ss1 x1 x2 pd784036(a) m (2) external clock ? when extc bit of osts = 1 ? when extc bit of osts = 0 pd784036(a) x1 x2 pd74hc04, etc. m m x1 x2 open pd784036(a) m caution when using the clock generator, to avoid problems caused by influences such as stray capacitance, run all wiring within the area indicated by the dotted lines according to the following rules: ? minimize the wiring length. ? wires must never cross other signal lines. ? wires must never run near a line carrying a large varying current. ? the grounding point of the capacitor of the oscillator must always be at the same potential as v ss1 . never connect the capacitor to a ground pattern carrying a large current. ? never extract a signal from the oscillator.
m pd784035(a), 784036(a) 31 7.3 real-time output port the real-time output port outputs data stored in the buffer, synchronized with a timer/counter 1 match interrupt or external interrupt. thus, pulse output that is free of jitter can be obtained. therefore, the real-time output port is best suited to applications (such as open-loop control over stepping motors) where an arbitrary pattern is output at arbitrary intervals. as shown in figure 7-4, the real-time output port is built around port 0 and the port 0 buffer register (p0h, p0l). figure 7-4. block diagram of real-time output port 4 4 4 p0l p0h buffer register 8 4 8 p00 p07 output latch (p0) real-time output port control register (rtpc) output trigger control circuit intp0 (externally) intc10 (from timer/counter 1) intc11 (from timer/counter 1) internal bus
m pd784035(a), 784036(a) 32 7.4 timers/counters three timer/counter units and one timer unit are incorporated. moreover, seven interrupt requests are supported, allowing these units to function as seven timer/counter units. table 7-2. timer/counter operation note the one-shot pulse output function makes the level of a pulse output active by software, and makes the level of a pulse output inactive by hardware (interrupt request signal). note that this function differs from the one-shot timer function of timer/counter 2. name timer/counter 0 timer/counter 1 timer/counter 2 timer 3 item count pulse width 8 bits - 16 bits operating mode interval timer 2ch 2ch 2ch 1ch external event counter - one-shot timer - - - function timer output 2ch - 2ch - toggle output - - pwm/ppg output - - one-shot pulse output note --- real-time output - -- pulse width measurement 1 input 1 input 2 inputs - number of interrupt requests 2 2 2 1
m pd784035(a), 784036(a) 33 figure 7-5. timer/counter block diagram timer/counter 0 timer/counter 1 timer/counter 2 timer 3 remark ovf: overflow flag to1 f xx /8 ovf to0 intp3 intp3 intc00 intc01 clear information prescaler selector timer register 0 (tm0) software trigger compare register (cr00) match match pulse output control compare register (cr01) edge detection capture register (cr02) f xx /8 ovf intp0 intp0 intc10 intc11 clear information prescaler selector timer register 1 (tm1/tm1w) event input compare register (cr10/cr10w) match match edge detection capture/compare register (cr11/cr11w) to real-time output port capture register (cr12/cr12w) to3 f xx /8 ovf to2 intp1 intp1 intc20 intc21 intp2/ci intp2 clear information prescaler selector timer register 2 (tm2/tm2w) edge detection edge detection compare register (cr20/cr20w) match match capture/compare register (cr21/cr21w) pulse output control capture register (cr22/cr22w) f xx /8 timer register 3 (tm3/tm3w) compare register (cr30/cr30w) prescaler csi clear match intc30
m pd784035(a), 784036(a) 34 7.5 pwm output (pwm0, pwm1) two channels of pwm (pulse width modulation) output circuitry with a resolution of 12 bits and a repetition frequency of 62.5 khz (f clk = 16 mhz) are incorporated. low or high active level can be selected for the pwm output channels, independently of each other. this output is best suited to dc motor speed control. figure 7-6. block diagram of pwm output unit internal bus pwm modulo register pwm control register (pwmc) reload control prescaler 8-bit down-counter pulse control circuit 4-bit counter output control pwmn (output pin) 1/256 f clk 84 16 8 pwmn 15 0 8 7 4 3 remark n = 0, 1
m pd784035(a), 784036(a) 35 7.6 a/d converter an analog/digital (a/d) converter having 8 multiplexed analog inputs (ani0-ani7) is incorporated. the successive approximation system is used for conversion. the result of conversion is held in the 8-bit a/d conversion result register (adcr). thus, speedy high-precision conversion can be achieved. (the conversion time is about 7.5 m s at f clk = 16 mhz.) a/d conversion can be started in any of the following modes: ? hardware start : conversion is started by means of trigger input (intp5). ? software start : conversion is started by means of bit setting the a/d converter mode register (adm). after conversion has started, one of the following modes can be selected: ? scan mode : multiple analog inputs are selected sequentially to obtain conversion data from all pins. ? select mode: a single analog input is selected at all times to enable conversion data to be obtained continuously. adm is used to specify the above modes, as well as the termination of conversion. when the result of conversion is transferred to adcr, an interrupt request (intad) is generated. using this feature, the results of conversion can be continuously transferred to memory by the macro service. figure 7-7. block diagram of a/d converter ani0 ani7 intp5 av ref1 av ss r/2 r r/2 8 8 8 input selector tap selector sample-and-hold circuit voltage comparator successive conver- sion register (sar) series resistor string control circuit a/ d converter mode register (adm) a/ d conversion result register (adcr) internal bus edge detector conversion trigger trigger enable intad ani1 ani2 ani3 ani4 ani5 ani6
m pd784035(a), 784036(a) 36 7.7 d/a converter two digital/analog (d/a) converter channels of voltage output type, having a resolution of 8 bits, are incorporated. an r-2r resistor ladder system is used for conversion. by writing the value to be subject to d/a conversion in the 8-bit d/a conversion value setting register (dacsn: n = 0, 1), the resulting analog value is output on anon (n = 0, 1). the range of the output voltages is determined by the voltages applied to the av ref2 and av ref3 pins. because of its high output impedance, no current can be obtained from an output pin. when the load impedance is low, insert a buffer amplifier between the load and the converter. the impedance of the anon pin goes high while the reset signal is low. dacsn is set to 0 after a reset is released. figure 7-8. block diagram of d/a converter selector internal bus dacsn dacen 2r 2r 2r 2r av ref3 av ref2 r r r anon remark n = 0, 1
m pd784035(a), 784036(a) 37 7.8 serial interface three independent serial interface channels are incorporated. ? asynchronous serial interface (uart)/three-wire serial i/o (ioe) 2 ? synchronous serial interface (csi) 1 ? three-wire serial i/o (ioe) ? two-wire serial i/o (ioe) so, communication with points external to the system and local communication within the system can be performed at the same time. (see figure 7-9 .) figure 7-9. example serial interfaces int sck0 sb0 v dd si so sck port int port [two-wire serial i/o] uart + three-wire serial i/o + two-wire serial i/o [three-wire serial i/o] rs-232-c driver/receiver port rxd txd so1 si1 sck1 intpm port sda scl intpn port note note slave pd784036(a) master m slave v dd [uart] note handshake line
m pd784035(a), 784036(a) 38 7.8.1 asynchronous serial interface/three-wire serial i/o (uart/ioe) two serial interface channels are available; for each channel, asynchronous serial interface mode or three-wire serial i/o mode can be selected. (1) asynchronous serial interface mode in this mode, 1-byte data is transferred after a start bit. a baud rate generator is incorporated to enable communication at a wide range of baud rates. moreover, the frequency of a clock signal applied to the asck pin can be divided to define a baud rate. with the baud rate generator, the baud rate conforming to the midi standard (31.25 kbps) can be obtained. figure 7-10. block diagram of asynchronous serial interface mode rxb, rxb2 txs, txs2 intst, intst2 intsr, intsr2 intser, intser2 1/2m f xx /2 asck, asck2 txd, txd2 rxd, rxd2 1/2 n+1 1/2m baud rate generator receive shift register receive buffer selector transmission control parity bit addition transmission shift register internal bus reception control parity check remark f xx : oscillator frequency or external clock input n = 0 to 11 m = 16 to 30
m pd784035(a), 784036(a) 39 (2) three-wire serial i/o mode in this mode, the master device makes the serial clock active to start transmission, then transfers 1-byte data in phase with the clock. this mode is designed for communication with a device incorporating a conventional synchronous serial interface. basically, three lines are used for communication: the serial clock line (sck) and the two serial data lines (si and so). in general, a handshake line is required to check the state of communication. figure 7-11. block diagram of three-wire serial i/o mode serial clock counter sio1, sio2 si1, si2 so1, so2 sck1, sck2 f xx /2 intcsi1, intcsi2 shift register output latch direction control circuit internal bus serial clock control circuit selector 1/m 1/2 n+1 interrupt signal generator remark f xx : oscillator frequency or external clock input n = 0 to 11 m = 1, 16 to 30
m pd784035(a), 784036(a) 40 7.8.2 synchronous serial interface (csi) with this interface, the master device makes the serial clock active to start transmission, then transfers 1-byte data in phase with the clock. figure 7-12. block diagram of synchronous serial interface remark f xx : oscillator frequency or external clock input internal bus direction control circuit selector shift register set reset output latch n-ch open-drain output enabled (when two-wire mode is used) serial clock counter interrupt signal generator n-ch open-drain output enabled (when two-wire mode is used) serial clock control circuit selector timer 3 output selector prescaler f xx /16 f xx /2 intcsi cls0 cls1 sck0/scl si0 so0/sda
m pd784035(a), 784036(a) 41 (1) three-wire serial i/o mode this mode is designed for communication with a device incorporating a conventional synchronous serial interface. basically, three lines are used for communication: the serial clock line (sck0) and serial data lines (si0 and so0). in general, a handshake line is required to check the state of communication. (2) two-wire serial i/o mode in this mode, 8-bit data is transferred using two lines: the serial clock line (scl) and serial data bus (sda). in general, a handshake line is required to check the communication state. 7.9 clock output function the frequency of the cpu clock signal can be divided for output to a point external to the system. moreover, the port can be used as a 1-bit port. the astb pin is also used for the clkout pin, so that when this function is used, the local bus interface cannot be used. figure 7-13. block diagram of clock output function clkout f clk f clk /2 f clk /4 f clk /8 f clk /16 selector output control enable output output level
m pd784035(a), 784036(a) 42 7.10 edge detection function the interrupt input pins (nmi, intp0-intp5) are used to apply not only interrupt requests but also trigger signals for the built-in circuits. as these pins are triggered by an edge (rising or falling) of an input signal, a function for edge detection is incorporated. moreover, a noise suppression function is provided to prevent erroneous edge detection caused by noise. table 7-3. noise suppression method for interrupt input pins note intp0 is used for sampling clock selection. 7.11 watchdog timer a watchdog timer is incorporated for cpu runaway detection. the watchdog timer, if not cleared by software within a specified interval, generates a nonmaskable interrupt. furthermore, once watchdog timer operation is enabled, it cannot be disabled by software. the user can specify whether priority is placed on an interrupt based on the watchdog timer or on an interrupt based on the nmi pin. figure 7-14. block diagram of watchdog timer pin detectable edge noise suppression method nmi rising edge or falling edge analog delay intp0-intp3 rising edge or falling edge, or both edges clock sampling note intp4, intp5 analog delay f clk /2 21 f clk intwdt f clk /2 20 f clk /2 19 f clk /2 17 timer clear signal selector
m pd784035(a), 784036(a) 43 8. interrupt function table 8-1 lists the interrupt request handling modes. these modes are selected by software. table 8-1. interrupt request handling modes 8.1 interrupt source an interrupt can be issued from any one of the interrupt sources listed in table 8-2: execution of brk and brkcs instructions, an operand error, or any of the 23 other interrupt sources. four levels of interrupt handling priority can be set. priority levels can be set to nest control during interrupt handling or to concurrently generate interrupt requests. nested macro services, however, are performed without suspension. when interrupt requests having the same priority level are generated, they are handled according to the default priority (fixed). (see table 8-2 .) handling mode handled by handling pc and psw contents vectored interrupt software branches to a handling routine for execution the pc and psw contents are pushed (arbitrary handling). to and popped from the stack. context switching automatically selects a register bank, and the pc and psw contents are saved to branches to a handling routine for execution and read from a fixed area in the (arbitrary handling). register bank. macro service firmware performs operations such as memory-to-i/o- maintained device data transfer (fixed handling).
m pd784035(a), 784036(a) 44 table 8-2. interrupt sources type default source internal/ macro priority name trigger external service software - brk instruction instruction execution - - brkcs instruction operand error when the mov stbc,#byte, mov wdm,#byte, or location instruction is executed, exclusive or of the byte operand and byte does not produce ffh. nonmaskable - nmi detection of edge input on the pin external - wdt watchdog timer overflow internal maskable 0 (highest) intp0 detection of edge input on the pin (tm1/tm1w capture trigger, external enabled tm1/tm1w event counter input) 1 intp1 detection of edge input on the pin (tm2/tm2w capture trigger, tm2/tm2w event counter input) 2 intp2 detection of edge input on the pin ( tm2/tm2w capture trigger, internal enabled tm2/tm2w event counter input) 3 intp3 detection of edge input on the pin (tm0 capture trigger, tm0 event counter input) 4 intc00 tm0-cr00 match signal issued 5 intc01 tm0-cr01 match signal issued 6 intc10 tm1-cr10 match signal issued (in 8-bit operation mode) tm1w-cr10w match signal issued (in 16-bit operation mode) 7 intc11 tm1-cr11 match signal issued (in 8-bit operation mode) tm1w-cr11w match signal issued (in 16-bit operation mode) 8 intc20 tm2-cr20 match signal issued (in 8-bit operation mode) tm2w-cr20w match signal issued (in 16-bit operation mode) 9 intc21 tm2-cr21 match signal issued (in 8-bit operation mode) tm2w-cr21w match signal issued (in 16-bit operation mode) 10 intc30 tm3-cr30 match signal issued (in 8-bit operation mode) tm3w-cr30w match signal issued (in 16-bit operation mode) 11 intp4 detection of edge input on the pin external enabled 12 intp5 detection of edge input on the pin 13 intad a/d converter processing completed (adcr transfer) internal enabled 14 intser asi0 reception error - 15 intsr asi0 reception completed or csi1 transfer completed enabled intcsi1 16 intst asi0 transmission completed 17 intcsi csi0 transfer completed 18 intser2 asi2 reception error - 19 intsr2 asi2 reception completed or csi2 transfer completed enabled intcsi2 20 (lowest) intst2 asi2 transmission completed remark asi: asynchronous serial interface csi: synchronous serial interface
m pd784035(a), 784036(a) 45 8.2 vectored interrupt when a branch to an interrupt handling routine occurs, the vector table address corresponding to the interrupt source is used as the branch address. interrupt handling by the cpu consists of the following operations: ? when a branch occurs : push the cpu status (pc and psw contents) to the stack. ? when control is returned: pop the cpu status (pc and psw contents) from the stack. to return control from the handling routine to the main routine, use the reti instruction. the branch destination addresses must be within the range of 0 to ffffh. table 8-3. vector table address interrupt source vector table address brk instruction 003eh operand error 003ch nmi 0002h wdt 0004h intp0 0006h intp1 0008h intp2 000ah intp3 000ch intc00 000eh intc01 0010h intc10 0012h intc11 0014h intc20 0016h intc21 0018h intc30 001ah intp4 001ch intp5 001eh intad 0020h intser 0022h intsr 0024h intcsi1 intst 0026h intcsi 0028h intser2 002ah intsr2 002ch intcsi2 intst2 002eh
m pd784035(a), 784036(a) 46 8.3 context switching when an interrupt request is generated, or when the brkcs instruction is executed, an appropriate register bank is selected by the hardware. then, a branch to a vector address stored in that register bank occurs. at the same time, the contents of the current program counter (pc) and program status word (psw) are stacked in the register bank. the branch address must be within the range of 0 to ffffh. figure 8-1. context switching caused by an interrupt request psw pc19-16 0000b pc15-0 <6> exchange <5> save <2> save <1> save <7> transfer (bits 8 to 11 of temporary register) register bank n (n = 0-7) temporary register ax bc r5 r4 r7 vp up r6 de h t u v wl switching between register banks (rbs0-rbs2 n) rss 0 ie 0 register bank (0-7) <4> <3> 8.4 macro service the macro service function enables data transfer between memory and special function registers (sfrs) without requiring the intervention of the cpu. the macro service controller accesses both memory and sfrs within the same transfer cycle to directly transfer data without having to perform data fetch. since the cpu status is neither saved nor restored, nor is data fetch performed, high-speed data transfer is possible. figure 8-2. macro service cpu sfr memory read write read write macro service controller internal bus
m pd784035(a), 784036(a) 47 8.5 examples of macro service applications (1) serial interface transmission transmission data storage buffer (memory) intst txs (sfr) txd data n data n - 1 data 2 data 1 internal bus transmission shift register transmission control each time a macro service request (intst) is generated, the next transmission data is transferred from memory to txs. when data n (last byte) has been transferred to txs (that is, once the transmission data storage buffer becomes empty), a vectored interrupt request (intst) is generated. (2) serial interface reception reception data storage buffer (memory) intsr rxb (sfr) rxd data n data n - 1 data 2 data 1 internal bus reception buffer reception shift register reception control each time a macro service request (intsr) is generated, reception data is transferred from rxb to memory. when data n (last byte) has been transferred to memory (that is, once the reception data storage buffer becomes full), a vectored interrupt request (intsr) is generated.
m pd784035(a), 784036(a) 48 (3) real-time output port intc10 and intc11 function as the output triggers for the real-time output ports. for these triggers, the macro service can simultaneously set the next output pattern and interval. therefore, intc10 and intc11 can be used to independently control two stepping motors. they can also be applied to pwm and dc motor control. match (sfr) intc10 p00-p03 (sfr) output pattern profile (memory) output timing profile (memory) p n p n? p 2 p 1 internal bus p0l output latch cr10 tm1 internal bus t n t n? t 2 t 1 each time a macro service request (intc10) is generated, a pattern and timing data are transferred to the buffer register (p0l) and compare register (cr10), respectively. when the contents of timer register 1 (tm1) and cr10 match, another intc10 is generated, and the p0l contents are transferred to the output latch. when tn (last byte) is transferred to cr10, a vectored interrupt request (intc10) is generated. for intc11, the same operation as that performed for intc10 is performed.
m pd784035(a), 784036(a) 49 9. local bus interface the local bus interface enables the connection of external memory and i/o devices (memory-mapped i/o). it supports a 1m-byte memory space. (see figure 9-1 .) figure 9-1. example of local bus interface data bus latch gate array for i/o expansion including centronics interface circuit, etc. rd wr refrq ad0-ad7 astb pseudo sram prom pd27c1001a pd784036(a) a16-a19 m m address bus data bus a8-a15 decoder kanji character generator pd24c1000 m 9.1 memory expansion by adding external memory, program memory or data memory can be expanded to one of seven sizes between 256 bytes and approximately 1m byte.
m pd784035(a), 784036(a) 50 9.2 memory space the 1m-byte memory space is divided into eight spaces, each having a logical address. each of these spaces can be controlled using the programmable wait and pseudo-static ram refresh functions. figure 9-2. memory space fffffh 80000h 7ffffh 40000h 3ffffh 20000h 1ffffh 10000h 0ffffh 0c000h 0bfffh 08000h 07fffh 04000h 03fffh 00000h 512k bytes 256k bytes 128k bytes 64k bytes 16k bytes 16k bytes 16k bytes 16k bytes
m pd784035(a), 784036(a) 51 9.3 programmable wait when the memory space is divided into eight spaces, a wait state can be separately inserted for each memory space while the rd or wr signal is active. this prevents the overall system efficiency from being degraded even when memory devices having different access times are connected. in addition, an address wait function that extends the astb signal active period is provided to assure a longer address decode time. (this function is set for the entire space.) 9.4 pseudo-static ram refresh function refresh is performed as follows: ? pulse refresh a bus cycle is inserted where a refresh pulse is output on the refrq pin at regular intervals. when the memory space is divided into eight, and a specified area is being accessed, refresh pulses can also be output on the refrq pin as the memory is being accessed. this can prevent the refresh cycle from suspending normal memory access. ? power-down self-refresh in standby mode, a low-level signal is output on the refrq pin to maintain the contents of pseudo-static ram. 9.5 bus hold function a bus hold function is provided to facilitate connection to devices such as a dma controller. suppose that a bus hold request signal (hldrq) is received from an external bus master. in this case, upon the completion of the bus cycle being performed at the reception, the address bus, address/data bus, astb, rd, and wr pins are placed in the high-impedance state, and the bus hold acknowledge signal (hldak) is made active to release the bus for the external bus master. while the bus hold function is being used, the external wait and pseudo-static ram refresh functions are disabled.
m pd784035(a), 784036(a) 52 10. standby function the standby function allows the power consumption of the chip to be reduced. the following standby modes are supported: ? halt mode : the cpu operation clock is stopped. by occasionally inserting the halt mode during normal operation, the overall average power consumption can be reduced. ? idle mode : the entire system is stopped, with the exception of the oscillator. this mode consumes only very little more power than stop mode, but normal program operation can be restored in almost as little time as that required to restore normal program operation from halt mode. ? stop mode : the oscillator is stopped. all operations in the chip stop, such that only leakage current flows. these modes can be selected by software. a macro service can be initiated in halt mode. figure 10-1. standby mode status transition stop (standby) idle (standby) request for masked interrupt halt (standby) nmi, intp4, intp5 input note 1 set stop reset input set idle reset input nmi, intp4, intp5 input note 1 oscillation settling time elapses wait for oscillation settling program operation macro service request end of one operation end of macro service macro service set halt reset input interrupt request note 2 macro service request end of one operation notes 1. intp4 and intp5 are applied when not masked. 2. only when the interrupt request is not masked remark nmi is enabled only by external input. the watchdog timer cannot be used to release one of the standby modes (stop, halt, or idle mode).
m pd784035(a), 784036(a) 53 11. reset function applying a low-level signal to the reset pin initializes the internal hardware (reset status). when the reset input makes a low-to-high transition, the following data is loaded into the program counter (pc): ? eight low-order bits of the pc : contents of location at address 0000h ? intermediate eight bits of the pc : contents of location at address 0001h ? four high-order bits of the pc : 0 the pc contents are used as a branch destination address. program execution starts from that address. therefore, a reset start can be performed from an arbitrary address. the contents of each register can be set by software, as required. the reset input circuit contains a noise eliminator to prevent malfunctions caused by noise. this noise eliminator is an analog delay sampling circuit. figure 11-1. accepting a reset reset (input) delay delay delay initialize pc execute instruction at reset start address internal reset signal start reset end reset for power-on reset, the reset signal must be held active until the oscillation settling time (approximately 40 ms) has elapsed. figure 11-2. power-on reset oscillation settling time delay initialize pc execute instruction at reset start address reset (input) internal reset signal end reset v dd
m pd784035(a), 784036(a) 54 12. instruction set (1) 8-bit instructions (the instructions enclosed in parentheses are implemented by a combination of operands, where a is described as r.) mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, shr, shl, ror4, rol4, dbnz, push, pop, movm, xchm, cmpme, cmpmne, cmpmnc, cmpmc, movbk, xchbk, cmpbke, cmpbkne, cmpbknc, cmpbkc, chkl, chkla table 12-1. instructions implemented by 8-bit addressing 2nd operand #byte a r saddr sfr !addr16 mem r3 [whl+] n none note 2 r' saddr' !!addr24 [saddrp] pswl [whl-] 1st operand [%saddrg] pswh a (mov) (mov) mov (mov) note 6 mov (mov) mov mov (mov) add note 1 (xch) xch (xch) note 6 (xch) (xch) xch (xch) (add) note 1 (add) note 1 (add) notes 1, 6 (add) note 1 add note 1 add note 1 (add) note 1 r mov (mov) mov mov mov mov ror note 3 mulu add note 1 (xch) xch xch xch xch divuw (add) note 1 add note 1 add note 1 add note 1 inc dec saddr mov (mov) note 6 mov mov inc add note 1 (add) note 1 add note 1 xch dec add note 1 dbnz sfr mov mov mov push add note 1 (add) note 1 add note 1 pop chkl chkla !addr16 mov (mov) mov !!addr24 add note 1 mem mov [saddrp] add note 1 [%saddrg] mem3 ror4 rol4 r3 mov mov pswl pswh b, c dbnz stbc, wdm mov [tde+] (mov) movbk note 5 [tdeC] (add) note 1 movm note 4 notes 1. addc, sub, subc, and, or, xor, and cmp are the same as add. 2. there is no second operand, or the second operand is not an operand address. 3. rol, rorc, rolc, shr, and shl are the same as ror. 4. xchm, cmpme, cmpmne, cmpmnc, and cmpmc are the same as movm. 5. xchbk, cmpbke, cmpbkne, cmpbknc, and cmpbkc are the same as movbk. 6. when saddr is saddr2 with this combination, an instruction with a short code exists.
m pd784035(a), 784036(a) 55 (2) 16-bit instructions (the instructions enclosed in parentheses are implemented by a combination of operands, where ax is described as rp.) movw, xchw, addw, subw, cmpw, muluw, mulw, divux, incw, decw, shrw, shlw, push, pop, addwg, subwg, pushu, popu, movtblw, macw, macsw, sacw table 12-2. instructions implemented by 16-bit addressing 2nd operand #word ax rp saddrp strp !addr16 mem [whl+] byte n none note 2 rp' saddrp' !!addr24 [saddrp] 1st operand [%saddrg] ax (movw) (movw) (movw) (movw) note 3 movw (movw) movw (movw) addw note 1 (xchw) (xchw) (xchw) note 3 (xchw) xchw xchw (xchw) (add) note 1 (addw) note 1 (addw) notes 1,3 (addw) note 1 rp movw (movw) movw movw movw movw shrw mulw note 4 addw note 1 (xchw) xchw xchw xchw shlw incw (addw) note 1 addw note 1 addw note 1 addw note 1 decw saddrp movw (movw) note 3 movw movw incw addw note 1 (addw) note 1 addw note 1 xchw decw addw note 1 sfrp movw movw movw push addw note 1 (addw) note 1 addw note 1 pop !addr16 movw (movw) movw movtblw !!addr24 mem movw [saddrp] [%saddrg] psw push pop sp addwg subwg post push pop pushu popu [tde+] (movw) sacw byte macw macsw notes 1. subw and cmpw are the same as addw. 2. there is no second operand, or the second operand is not an operand address. 3. when saddrp is saddrp2 with this combination, an instruction with a short code exists. 4. muluw and divux are the same as mulw.
m pd784035(a), 784036(a) 56 (3) 24-bit instructions (the instructions enclosed in parentheses are implemented by a combination of operands, where whl is described as rg.) movg, addg, subg, incg, decg, push, pop table 12-3. instructions implemented by 24-bit addressing 2nd operand #imm24 whl rg saddrg !!addr24 mem1 [%saddrg] sp none note 1st operand rg' whl (movg) (movg) (movg) (movg) (movg) movg movg movg (addg) (addg) (addg) addg (subg) (subg) (subg) subg rg movg (movg) movg movg movg incg addg (addg) addg decg subg (subg) subg push pop saddrg (movg) movg !!addr24 (movg) movg mem1 movg [%saddrg] movg sp movg movg incg decg note there is no second operand, or the second operand is not an operand address.
m pd784035(a), 784036(a) 57 (4) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, btclr, bfset table 12-4. bit manipulation instructions implemented by addressing 2nd operand cy saddr.bit sfr.bit /saddr.bit /sfr.bit none note a.bit x.bit /a.bit /x.bit pswl.bit pswh.bit /pswl.bit /pswh.bit mem2.bit /mem2.bit 1st operand !addr16.bit !!addr24.bit /!addr16.bit /!!addr24.bit cy mov1 and1 not1 and1 or1 set1 or1 clr1 xor1 saddr.bit mov1 not1 sfr.bit set1 a.bit clr1 x.bit bf pswl.bit bt pswh.bit btclr mem2.bit bfset !addr16.bit !!addr24.bit note there is no second operand, or the second operand is not an operand address.
m pd784035(a), 784036(a) 58 (5) call/return instructions and branch instructions call, callf, callt, brk, ret, reti, retb, retcs, retcsb, brkcs, br, bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz table 12-5. call/return and branch instructions implemented by addressing instruction $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] rbn none address operand basic bc note call call call call call call call callf callf brkcs brk instruction br br br br br br br br ret retcs reti retcsb retb composite bf instruction bt btclr bfset dbnz note bnz, bne, bz, be, bnc, bnl, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, and bh are the same as bc. (6) other instructions adjba, adjbs, cvtbw, location, sel, not ei, di, swrs
m pd784035(a), 784036(a) 59 13. electrical characteristics absolute maximum ratings (t a = 25 c) parameter symbol conditions rating unit supply voltage v dd -0.5 to +7.0 v av dd av ss to v dd + 0.5 v av ss -0.5 to +0.5 v input voltage v i -0.5 to v dd + 0.5 v output voltage v o -0.5 to v dd + 0.5 v output low current i ol at one pin 15 ma total of all output pins 100 ma output high current i oh at one pin -10 ma total of all output pins -100 ma a/d converter reference input av ref1 -0.5 to v dd + 0.3 v voltage av ref2 -0.5 to v dd + 0.3 v av ref3 -0.5 to v dd + 0.3 v operating ambient temperature t a -40 to +85 c storage temperature t stg -65 to +150 c d/a converter reference input voltage caution absolute maximum ratings are rated values beyond which physical damage will be caused to the product; if the rated value of any of the parameters in the above table is exceeded, even momentarily, the quality of the product may deteriorate. always use the product within its rated values.
m pd784035(a), 784036(a) 60 operating conditions ? operating ambient temperature (t a ) : -40 to +85 c ? rise time and fall time (t r , t f ) (at pins which are not specified) : 0 to 200 m s ? power supply voltage and clock cycle time : see figure 13-1. figure 13-1. power supply voltage and clock cycle time capacitance (t a = 25 c, v dd = v ss = 0 v) parameter input capacitance output capacitance i/o capacitance symbol c i c o c io conditions f = 1 mhz 0 v on pins other than measured pins min. typ. max. 10 10 10 unit pf pf pf 10 000 4 000 1 000 125 100 62.5 10 01234567 guaranteed operating range power supply voltage [v] clock cycle time t cyk [ns]
m pd784035(a), 784036(a) 61 oscillator characteristics (t a = -40 to +85 c, v dd = +4.5 to 5.5 v, v ss = 0 v) caution when using the system clock generator, run wires in the portion surrounded by broken lines according to the following rules to avoid effects such as stray capacitance: minimize the wiring. never cause the wires to cross other signal lines. never cause the wires to run near a line carrying a large varying current. cause the grounding point of the capacitor of the oscillator to have the same potential as v ss1 . never connect the capacitor to a ground pattern carrying a large current. never extract a signal from the oscillator. resonator ceramic resonator or crystal external clock recommended circuit min. 4 4 0 10 max. 32 32 10 125 unit mhz mhz ns ns x1 x2 hcmos inverter parameter oscillator frequency (f xx ) x1 input frequency (f x ) x1 input rise and fall times (t xr , t xf ) x1 input high-level and low- level widths (t wxh , t wxl ) v ss1 x1 x2 c2 c1
m pd784035(a), 784036(a) 62 oscillator characteristics (t a = -40 to +85 c, v dd = +2.7 to 5.5 v, v ss = 0 v) caution when using the system clock generator, run wires in the portion surrounded by broken lines according to the following rules to avoid effects such as stray capacitance: minimize the wiring. never cause the wires to cross other signal lines. never cause the wires to run near a line carrying a large varying current. cause the grounding point of the capacitor of the oscillator to have the same potential as v ss1 . never connect the capacitor to a ground pattern carrying a large current. never extract a signal from the oscillator. resonator ceramic resonator or crystal external clock recommended circuit parameter oscillator frequency (f xx ) x1 input frequency (f x ) x1 input rise and fall times (t xr , t xf ) x1 input high-level and low- level widths (t wxh , t wxl ) min. 4 4 0 10 max. 16 16 10 125 unit mhz mhz ns ns x1 x2 hcmos inverter v ss1 x1 x2 c2 c1
m pd784035(a), 784036(a) 63 dc characteristics (t a = -40 to +85 c, v dd = av dd = +2.7 to 5.5 v, v ss = av ss = 0 v) (1/2) notes 1. x1, x2, reset, p12/asck2/sck2, p20/nmi, p21/intp0, p22/intp1, p23/intp2/ci, p24/intp3, p25/intp4/asck/sck1, p26/intp5, p27/si0, p32/sck0/scl, p33/so0/sda, test 2. p40/ad0-p47/ad7, p50/a8-p57/a15 3. p60/a16-p63/a19, p64/rd, p65/wr, p66/wait/hldrq, p67/refrq/hldak 4. p00-p07 5. p10-p17 parameter input low voltage input high voltage output low voltage output high voltage x1 input low current x1 input high current symbol v il1 v il2 v il3 v ih1 v ih2 v ih3 v ol1 v ol2 v oh1 v oh2 i il i ih conditions for pins other than those described in notes 1, 2, 3, and 4 for pins described in notes 1, 2, 3, and 4 v dd = +5.0 v 10 % for pins described in notes 2, 3, and 4 for pins other than those described in note 1 for pins described in note 1 v dd = +5.0 v 10 % for pins described in notes 2, 3, and 4 i ol = 2 ma v dd = +5.0 v 10 % i ol = 8 ma for pins described in notes 2 and 5 i oh = -2 ma v dd = +5.0 v 10 % i oh = -5 ma for pins described in note 4 extc = 0 0 v v i v il2 extc = 0 v ih2 v i v dd min. -0.3 -0.3 -0.3 0.7v dd 0.8v dd 2.2 v dd - 1.0 v dd - 1.4 typ. max. 0.3v dd 0.2v dd +0.8 v dd + 0.3 v dd + 0.3 v dd + 0.3 0.4 1.0 -30 +30 unit v v v v v v v v v v m a m a
m pd784035(a), 784036(a) 64 dc characteristics (t a = -40 to +85 c, v dd = av dd = +2.7 to 5.5 v, v ss = av ss = 0 v) (2/2) parameter input leakage current output leakage current v dd supply current pull-up resistor symbol i li i lo i dd1 i dd2 i dd3 r l conditions 0 v v i v dd for pins other than x1 when extc = 0 0 v v o v dd operation mode f xx = 32 mhz v dd = +5.0 v 10 % f xx = 16 mhz v dd = +2.7 to 3.3 v halt mode f xx = 32 mhz v dd = +5.0 v 10 % f xx = 16 mhz v dd = +2.7 to 3.3 v idle mode f xx = 32 mhz (extc = 0) v dd = +5.0 v 10 % f xx = 16 mhz v dd = +2.7 to 3.3 v v i = 0 v min. 15 typ. 25 12 13 8 max. 10 10 45 25 26 12 12 8 80 unit m a m a ma ma ma ma ma ma k w
m pd784035(a), 784036(a) 65 ac characteristics (t a = -40 to +85 c, v dd = av dd = +2.7 to 5.5 v, v ss = av ss = 0 v) (1) read/write operation (1/2) remarks t: t cyk (system clock cycle time) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 0) unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter address setup time astb high-level width address hold time (to astb ? ) address hold time (to rd ) delay from address to rd ? address float time (to rd ? ) delay from address to data input delay from astb ? to data input delay from rd ? to data input delay from astb ? to rd ? data hold time (to rd ) delay from rd to address active delay from rd to astb rd low-level width address hold time (to wr ) delay from address to wr ? delay from astb ? to data output delay from wr ? to data output delay from astb ? to wr ? symbol t sast t wsth t hstla t hra t dar t fra t daid t dstid t drid t dstr t hrid t dra t drst t wrl t hwa t daw t dstod t dwod t dstw min. (0.5 + a) t - 15 (0.5 + a) t - 31 (0.5 + a) t - 17 (0.5 + a) t - 40 0.5t - 24 0.5t - 34 0.5t - 14 (1 + a) t - 9 (1 + a) t - 15 0.5t - 9 0 0.5t - 8 0.5t - 12 1.5t - 8 1.5t - 12 0.5t - 17 (1.5 + n) t - 30 (1.5 + n) t - 40 0.5t - 14 (1 + a) t - 5 (1 + a) t - 15 0.5t - 9 max. 0 (2.5 + a + n) t - 37 (2.5 + a + n) t - 52 (2 + n) t - 40 (2 + n) t - 60 (1.5 + n) t - 50 (1.5 + n) t - 70 0.5t + 19 0.5t + 35 0.5t - 11 after program is read after data is read conditions v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 %
m pd784035(a), 784036(a) 66 (1) read/write operation (2/2) note the hold time includes the time during which v oh1 and v ol1 are held under the load conditions of c l = 50 pf and r l = 4.7 k w . remarks t: t cyk (system clock cycle time) n: number of wait states (n 0) (2) bus hold timing remarks t: t cyk (system clock cycle time) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 0) unit ns ns ns ns ns ns ns parameter data setup time (to wr ) data hold time (to wr ) note delay from wr to astb wr low-level width symbol t sodw t hwod t dwst t wwl min. (1.5 + n) t - 30 (1.5 + n) t - 40 0.5t - 5 0.5t - 25 0.5t - 12 (1.5 + n) t - 30 (1.5 + n) t - 40 max. conditions v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % unit ns ns ns ns ns ns ns ns parameter delay from hldrq to float delay from hldrq to hldak delay from float to hldak delay from hldrq ? to hldak ? delay from hldak ? to active min. 1t - 20 1t - 30 max. (6 + a + n) t + 50 (7 + a + n) t + 30 (7 + a + n) t + 40 1t + 30 2t + 40 2t + 60 conditions v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % symbol t fhqc t dhqhhah t dcfha t dhqlhal t dhac
m pd784035(a), 784036(a) 67 (3) external wait timing remarks t: t cyk (system clock cycle time) a: 1 (during address wait), otherwise, 0 n: number of wait states (n 0) (4) refresh timing remark t: t cyk (system clock cycle time) parameter delay from address to wait ? input delay from astb ? to wait ? input hold time from astb ? to wait delay from astb ? to wait delay from rd ? to wait ? input hold time from rd ? to wait ? delay from rd ? to wait delay from wait to data input delay from wait to wr delay from wait to rd delay from wr ? to wait ? input hold time from wr ? to wait delay from wr ? to wait unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns min. (0.5 + n) t + 5 (0.5 + n) t +10 nt + 5 nt + 10 0.5t 0.5t nt + 5 nt + 10 max. (2 + a) t - 40 (2 + a) t - 60 1.5t - 40 1.5t - 60 (1.5 + n) t - 40 (1.5 + n) t - 60 t - 50 t - 70 (1 + n) t - 40 (1 + n) t - 60 0.5t - 5 0.5t - 10 t - 50 t - 75 (1 + n) t - 40 (1 + n) t - 70 conditions v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % symbol t dawt t dstwt t hstwth t dstwth t drwtl t hrwt t drwth t dwtid t dwtw t dwtr t dwwtl t hwwt t dwwth unit ns ns ns ns ns ns ns ns ns parameter random read/write cycle time refrq low-level pulse width delay from astb ? to refrq delay from rd to refrq delay from wr to refrq delay from refrq to astb refrq high-level pulse width max. min. 3t 1.5t - 25 1.5t - 30 0.5t - 9 1.5t - 9 1.5t - 9 0.5t - 15 1.5t - 25 1.5t - 30 symbol t rc t wrfql t dstrfq t drrfq t dwrfq t drfqst t wrfqh conditions v dd = +5.0 v 10 % v dd = +5.0 v 10 %
m pd784035(a), 784036(a) 68 serial operation (t a = -40 to +85 c, v dd = +2.7 to 5.5 v, av ss = v ss = 0 v) (1) csi remarks 1. the values in this table are those when c l is 100 pf. 2. t : serial clock cycle set by software. the minimum value is 16/f xx . 3. f xx : oscillator frequency unit ns m s ns m s ns m s ns ns ns ns parameter serial clock cycle time (sck0) serial clock low-level width (sck0) serial clock high-level width (sck0) si0 setup time (to sck0 ) si0 hold time (to sck0 ) so0 output delay time (to sck0 ? ) min. 10/f xx + 380 t 5/f xx + 150 0.5t - 40 5/f xx + 150 0.5t - 40 40 5/f xx + 40 0 0 max. 5/f xx + 150 5/f xx + 400 conditions input external clock when sck0 and so0 are cmos i/o output input external clock when sck0 and so0 are cmos i/o output input external clock when sck0 and so0 are cmos i/o output cmos push-pull output (3-wire serial i/o mode) open-drain output (2-wire serial i/o mode), r l = 1 k w symbol t cysk0 t wskl0 t wskh0 t sssk0 t hssk0 t dsbsk1 t dsbsk2
m pd784035(a), 784036(a) 69 parameter serial clock cycle time (sck1, sck2) serial clock low-level width (sck1, sck2) serial clock high-level width (sck1, sck2) setup time for si1 and si2 (to sck1, sck2 ) hold time for si1 and si2 (to sck1, sck2 ) output delay time for so1 and so2 (to sck1, sck2 ? ) output hold time for so1 and so2 (to sck1, sck2 ) (2) ioe1, ioe2 remarks 1. the values in this table are those when c l is 100 pf. 2. t: serial clock cycle set by software. the minimum value is 16/f xx . (3) uart, uart2 unit ns ns ns ns ns ns ns ns ns ns ns ns ns min. 250 500 t 85 210 0.5t - 40 85 210 0.5t - 40 40 40 0 0.5t cysk1 - 40 max. 50 symbol t cysk1 t wskl1 t wskh1 t sssk1 t hssk1 t dsosk t hsosk conditions input v dd = +5.0 v 10 % output internal, divided by 16 input v dd = +5.0 v 10 % output internal, divided by 16 input v dd = +5.0 v 10 % output internal, divided by 16 when data is transferred unit ns ns ns ns ns ns parameter asck clock input cycle time asck clock low-level width asck clock high-level width symbol t cyask t waskl t waskh min. 125 250 52.5 85 52.5 85 max. conditions v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 %
m pd784035(a), 784036(a) 70 clock output operation remarks n: divided frequency ratio set by software in the cpu (n = 1, 2, 4, 8, 16) t: t cyk (system clock cycle time) other operations remarks t cysmp : sampling clock set by software t cycpu : cpu operation clock set by software in the cpu unit m s m s ns ns ns ns m s m s m s m s parameter nmi low-level width nmi high-level width intp0 low-level width intp0 high-level width low-level width for intp1- intp3 and ci high-level width for intp1- intp3 and ci low-level width for intp4 and intp5 high-level width for intp4 and intp5 reset low-level width reset high-level width symbol t wnil t wnih t wit0l t wit0h t wit1l t wit1h t wit2l t wit2h t wrsl t wrsh min. 10 10 4t cysmp 4t cysmp 4t cycpu 4t cycpu 10 10 10 10 max. conditions unit ns ns ns ns ns ns ns ns ns parameter clkout cycle time clkout low-level width clkout high-level width clkout rise time clkout fall time min. nt 0.5t cycl - 10 0.5t cycl - 20 0.5t cycl - 10 0.5t cycl - 20 max. 10 20 10 20 conditions v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % v dd = +5.0 v 10 % symbol t cycl t cll t clh t clr t clf
m pd784035(a), 784036(a) 71 conditions fr = 1 fr = 0 fr = 1 fr = 0 f xx = 32 mhz, cs = 1 stop mode, cs = 0 a/d converter characteristics (t a = -40 to +85 c, v dd = av dd = av ref1 = +2.7 to 5.5 v, v ss = av ss = 0 v) note quantization error is not included. this parameter is indicated as the ratio to the full-scale value. remark t cyk : system clock cycle time min. 8 120 180 24 36 -0.3 typ. 1 000 0.5 2.0 1.0 max. 1.0 0.8 1/2 av ref1 + 0.3 1.5 5.0 20 symbol t conv t samp v ian r an ai ref1 ai dd1 ai dd2 parameter resolution total error note linearity calibration note quantization error conversion time sampling time analog input voltage analog input impedance av ref1 current av dd supply current unit bit % % lsb t cyk t cyk t cyk t cyk v m w ma ma m a
m pd784035(a), 784036(a) 72 d/a converter characteristics (t a = -40 to +85 c, v dd = av dd = +2.7 to 5.5 v, v ss = av ss = 0 v) parameter resolution total error settling time output resistance analog reference voltage resistance of av ref2 and av ref3 reference power supply input current symbol r o av ref2 av ref3 r airef ai ref2 ai ref3 conditions load conditions: v dd = av dd = av ref2 4 m w , 30 pf = +2.7 to 5.5 v av ref3 = 0 v v dd = av dd = +2.7 to 5.5 v av ref2 = 0.75v dd av ref3 = 0.25v dd load conditions: v dd = av dd = av ref2 2 m w , 30 pf = +2.7 to 5.5 v av ref3 = 0 v v dd = av dd = +2.7 to 5.5 v av ref2 = 0.75v dd av ref3 = 0.25v dd load conditions: 2 m w , 30 pf dacs0, 1 = 55 h dacs0, 1 = 55 h min. 8 0.75v dd 0 4 0 -5 typ. 10 8 max. 0.6 0.8 0.8 1.0 10 v dd 0.25v dd 5 0 unit bit % % % % m s k w v v k w ma ma
m pd784035(a), 784036(a) 73 data retention characteristics (t a = -40 to +85 c) note reset, p20/nmi, p21/intp0, p22/intp1, p23/intp2/ci, p24/intp3, p25/intp4/asck/sck1, p26/intp5, p27/si0, p32/sck0/scl, and p33/so0/sda pins ac timing test points parameter data retention voltage data retention current v dd rise time v dd fall time v dd hold time (to stop mode setting) stop clear signal input time oscillation settling time input low voltage input high voltage conditions stop mode v dddr = +2.7 to 5.5 v v dddr = +2.5 v crystal ceramic resonator specific pins note min. 2.5 200 200 0 0 30 5 0 0.9v dddr typ. 10 2 max. 5.5 50 10 0.1v dddr v dddr unit v m a m a m s m s ms ms ms ms v v symbol v dddr i dddr t rvd t fvd t hvd t drel t wait v il v ih 0.8v dd or 2.2 v 0.8 v 0.8v dd or 2.2 v 0.8 v test points v dd - 1 v 0.45 v
m pd784035(a), 784036(a) 74 timing waveform (1) read operation (2) write operation astb a8-a19 ad0-ad7 rd t wsth t sast t dstid t hstla t drst t fra t drid t dar t wrl t dstr t daid t hra t dra t hrid astb a8-a19 ad0-ad7 wr t wsth t sast t hstla t dwst t daw t dstw t hwod t dstod t dwod t sodw t wwl t hwa
m pd784035(a), 784036(a) 75 hold timing external wait signal input timing (1) read operation (2) write operation hldrq hldak t dhqhhah t fhqc t dcfha t dhac t dhqlhal adtb, a8-a19, ad0-ad7, rd, wr astb a8-a19 ad0-ad7 rd wait t dstwt t hstwth t dstwth t dawt t dwtid t dwtr t drwtl t hrwt t drwth astb a8-a19 ad0-ad7 wr wait t dstwt t hstwth t dstwth t dawt t dwtw t dwwtl t hwwt t dwwth
m pd784035(a), 784036(a) 76 refresh timing waveform (1) random read/write cycle (2) when refresh memory is accessed for a read and write at the same time (3) refresh after a read (4) refresh after a write astb wr rd t rc t rc t rc t rc t rc t wrfql astb rd, wr refrq t dstrfq t drfqst t wrfqh astb rd refrq t drfqst t drrfq t wrfql astb wr refrq t drfqst t dwrfq t wrfql
m pd784035(a), 784036(a) 77 serial operation (1) csi (2) ioe1, ioe2 (3) uart, uart2 sck si so output data input data t sssk0 t hssk0 t dsbsk1 t wskl0 t wskh0 t hsbsk1 t cysk0 sck si so output data input data t sssk1 t hssk1 t dsosk t hsosk t wskl1 t wskh1 t cysk1 asck, asck2 t waskh t waskl t cyask
m pd784035(a), 784036(a) 78 clock output timing interrupt request input timing reset input timing nmi intp0 ci, intp1-intp3 intp4, intp5 t wnih t wnil t wit0h t wit0l t wit1h t wit1l t wit2h t wit2l reset t wrsh t wrsl clkout t clh t cll t cycl t clf t clr
m pd784035(a), 784036(a) 79 external clock timing data retention characteristics v dd reset nmi (clearing by falling edge) nmi (clearing by rising edge) t hvd t fvd t rvd t drel v dddr stop mode setting t wait x1 t wxh t wxl t cyx t xf t xr
m pd784035(a), 784036(a) 80 14. package drawings remark the shape and material of the es version are the same as those of the corresponding mass-produced product. 80 pin plastic qfp (14x14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. l 0.8 0.2 0.031 +0.009 ?.008 m 0.15 0.006 n 0.10 0.004 a 17.2 0.4 0.677 0.016 b 14.0 0.2 0.551 +0.009 ?.008 c 14.0 0.2 0.551 +0.009 ?.008 d 17.2 0.4 0.677 0.016 f 0.825 0.032 g 0.825 0.032 h 0.30 0.10 0.012 +0.004 ?.005 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) q 0.1 0.1 0.004 0.004 r5 5 5 5 +0.10 ?.05 +0.004 ?.003 m m l k j h q p n r detail of lead end i g k 1.6 0.2 0.063 0.008 60 61 40 80 1 21 20 41 a b cd f s s80gc-65-3b9-5 s 3.0 max. 0.119 max. p 2.7 0.1 0.106 +0.005 ?.004
m pd784035(a), 784036(a) 81 15. recommended soldering conditions the conditions listed below shall be met when soldering the m pd784035(a) and m pd784036(a). for details of the recommended soldering conditions, refer to our document semiconductor device mounting technology manual (c10535e) . please consult with our sales offices in case any other soldering process is used, or in case soldering is done under different conditions. table 15-1. soldering conditions for surface-mount devices m pd784035gc(a)- -3b9: 80-pin plastic qfp (14 14 mm) m pd784036gc(a)- -3b9: 80-pin plastic qfp (14 14 mm) caution do not apply two or more different soldering methods to one chip (except for partial heating method for terminal sections). soldering process soldering conditions symbol infrared ray reflow peak package's surface temperature: 235 c ir35-00-3 reflow time: 30 seconds or less (210 c or more) maximum allowable number of reflow processes: 3 vps peak package's surface temperature: 215 c vp15-00-3 reflow time: 40 seconds or less (200 c or more) maximum allowable number of reflow processes: 3 wave soldering solder temperature: 260 c or less ws60-00-1 flow time: 10 seconds or less number of flow processes: 1 preheating temperature : 120 c max. (measured on the package surface) partial heating method terminal temperature: 300 c or less - heat time: 3 seconds or less (for one side of a device)
m pd784035(a), 784036(a) 82 appendix a development tools the following development tools are available for system development using the m pd784036(a). see also (5) . (1) language processing software ra78k4 assembler package for all 78k/iv series models cc78k4 c compiler package for all 78k/iv series models df784038 device file for m pd784038 sub-series models cc78k4-l c compiler library source file for all 78k/iv series models (2) prom write tools pg-1500 prom programmer pa-78p4026gc programmer adaptor, connects to pg-1500 pg-1500 controller control program for pg-1500 (3) debugging tools ? when using the in-circuit emulator ie-78k4-ns ie-78k4-ns note in-circuit emulator for all 78k/iv series models ie-70000-mc-ps-b power supply unit for ie-78k4-ns ie-70000-98-if-c note interface adapter when the pc-9800 series computer (other than a notebook) is used as the host machine ie-70000-cd-if note pc card and interface cable when a pc-9800 series notebook is used as the host machine ie-70000-pc-if-c note interface adapter when the ibm pc/at tm or compatible is used as the host machine ie-784038-ns-em1 note emulation board for evaluating m pd784038 sub-series models np-80gc emulation probe for 80-pin plastic qfp (gc-3b9 type) ev-9200gc-80 socket for mounting on target system board made for 80-pin plastic qfp (gc-3b9 type) id78k4-ns note integrated debugger for ie-78k4-ns sm78k4-ns system simulator for all 78k/iv series models df784038 device file for m pd784038 sub-series models note under development
m pd784035(a), 784036(a) 83 ? when using the in-circuit emulator ie-784000-r ie-784000-r in-circuit emulator for all 78k/iv series models ie-70000-98-if-b interface adapter when the pc-9800 series computer (other than a notebook) ie-70000-98-if-c note is used as the host machine ie-70000-98n-if-b interface adapter and cable when a pc-9800 series notebook is used as the host machine ie-70000-pc-if-b interface adapter when the ibm pc/at or compatible is used as the host ie-70000-pc-if-c note machine ie-78000-r-sv3 interface adapter and cable when the ews is used as the host machine ie-784038-ns-em1 note emulation board for evaluating m pd784038 sub-series models ie-784038-r-em1 note ie-78400-r-em emulation board for all 78k/iv series models ie-78k4-r-ex2 note conversion board for 80 pins to use the ie-784038-ns-em1 on the ie-784000-r. the board is not needed when the conventional product ie-784038-r-em1 is used. ep-78230gc-r emulation probe for 80-pin plastic qfp (gc-3b9 type) ev-9200gc-80 socket for mounting on target system board made for 80-pin plastic qfp (gc-3b9 type) id78k4 integrated debugger for ie-784000-r sm78k4 system simulator for all 78k/iv series models df784038 device file for m pd784038 sub-series models note under development (4) real-time os rx78k/iv real-time os for 78k/iv series models mx78k4 os for 78k/iv series models
m pd784035(a), 784036(a) 84 (5) notes when using development tools ? the id78k-ns, id78k4, and sm78k4 can be used in combination with the df784038. ? the cc78k and rx78k/iv can be used in combination with the ra78k4 and df784038. ? the np-80gc is a product from naito densei machida seisakusho co., ltd. (044-822-3813). consult the nec sales representative for purchasing. ? the host machines and operating systems corresponding to each software are shown below. host machine pc ews [os] pc-9800 series [windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at and compatibles [windows] sparcstation tm [sunos tm ] news tm (risc) [news-os tm ] software ra78k4 note cc78k4 note pg-1500 controller note - id78k4-ns - id78k4 sm78k4 - rx78k/iv note mx78k4 note note software under ms-dos
m pd784035(a), 784036(a) 85 appendix b related documents documents related to devices document name document no. japanese english m pd784035(a), 784036(a) data sheet u13010j this manual m pd784031(a) data sheet u13009j under creation m pd78p4038(a) data sheet to be created to be created m pd784038, 784038y sub-series user's manual, hardware u11316j u11316e m pd784038 sub-series special function registers u11090j - 78k/iv series user's manual, instruction u10905j u10905e 78k/iv series instruction summary sheet u10594j - 78k/iv series instruction set u10595j - 78k/iv series application note, software basic u10095j - documents related to development tools (users manual) document name document no. japanese english ra78k4 assembler package operation u11334j u11334e language u11162j u11162e ra78k series structured assembler preprocessor u11743j u11743e cc78k4 c compiler operation u11572j u11572e language u11571j u11571e cc78k series library source file u12322j u12322e pg-1500 prom programmer u11940j u11940e pg-1500 controller pc-9800 series (ms-dos tm ) base eeu-704 eeu-1291 pg-1500 controller ibm pc series (pc dos tm ) base eeu-5008 u10540e ie-78k4-ns under creation to be created ie-784000-r u12903j eeu-1534 ie-784038-ns-em1 to be created to be created ie-784038-r-em1 u11383j u11383e ep-78230 eeu-985 eeu-1515 sm78k4 system simulator windows base reference u10093j u10093e sm78k series system simulator external parts user open u10092j u10092e interface specifications id78k4 integrated debugger reference u12796j u12796e id78k4 integrated debugger windows base reference u10440j u10440e id78k4 integrated debugger hp-ux, sunos, new-os base reference u11960j u11960e caution the above documents may be revised without notice. use the latest versions when you design application systems.
m pd784035(a), 784036(a) 86 documents related to software to be incorporated into the product (user?s manual) document name document no. japanese english 78k/iv series real-time os basic u10603j u10603e installation u10604j u10604e debugger u10364j - os for 78k/iv series mx78k4 basic u11779j - other documents document name document no. japanese english ic package manual c10943x semiconductor mount technology manual c10535j c10535e quality grades on nec semiconductor device c11531j c11531e nec semiconductor device reliability/quality control system c10983j c10983e guide to prevent damage for semiconductor devices by electrostatic discharge (esd) u11892j e11892e semiconductor device quality control/reliability handbook c12769j - guide for products related to micro-computer: other companies c11416j - caution the above documents may be revised without notice. use the latest versions when you design application systems.
m pd784035(a), 784036(a) 87 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
m pd784035(a), 784036(a) 88 iebus is a trademark of nec corporation. ms-dos and windows are registered trademarks or trademarks of microsoft corporation in the united states and/or other countries. pc/at, and pc dos are trademarks of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems, inc. news and news-os are trademarks of sony corporation.
m pd784035(a), 784036(a) 89 regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.1. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. spain office madrid, spain tel: 01-504-2787 fax: 01-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore 1130 tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-719-2377 fax: 02-719-5951 nec do brasil s.a. cumbica-guarulhos-sp, brasil tel: 011-6465-6810 fax: 011-6465-6829 j97. 8
m pd784035(a), 784036(a) some related documents may be preliminary versions. note that, however, what documents are preliminary is not indicated in this document. the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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